Descriptions of the Figures

MICROCOMPUTER WITH DISCONNECTED, OPEN, INDEPENDENT, BIMEMORY ARCHITECTURE, ALLOWING LARGE INTERACTING, INTERCONNECTED MULTI-MICROCOMPUTER PARALLEL SYSTEMS ACCOMMODATING MULTIPLE LEVELS OF PROGRAMMER DEFINED HIERARCHY

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a general diagram of one simple bimemory switching circuit according to the invention, in one of the dedicated standard memory circuits between the CPU and the "A" bus circuits, the "B" bus circuits and the "C" bus circuits. There is one such bimemory switching circuit connected in each BICPU microcomputer dedicated standard memory address circuit, standard memory data circuit and standard memory control circuit.

FIG. 2 illustrates the logically disconnected and latched positions of the five major switch means in the bimemory switching circuits and the logically disconnected and latched, floating circuits of the first and second switch means in the automatic power off deactivated mode. This logically disconnected and latched, power off deactivated mode is an object of the invention.

Each of FIGS. 3 through 13 and 15 through 17 illustrate the logically disconnected and latched positions or the logically connected and latched positions or the logically connected and unlatched logical bimemory hookup positions of the third through seventh switch means in the bimemory switching circuits, controlled by the CPU 202 to place the BICPU microcomputer in fifteen different logical bimemory modes, when power is being supplied to the power circuits.

FIG. 3 represents the PRM-0 mode.

FIG. 4 represents the PRM-1 and PRM-2 modes.

FIG. 5 represents the BIM-0 mode.

FIG. 6 represents the BIM-1 mode.

FIG. 7 represents the BIM-2 mode.

FIG. 8 represents the BIM-3 mode.

FIG. 9 represents the BIM-4 mode.

FIG. 10 represents the BIM-5 mode.

FIG. 11 represents the BIM-6 mode.

FIG. 12 represents the BIM-7 mode.

FIG. 13 represents the FLT-0 mode.

FIG. 14 is an illustration of the logically disconnected and latched switch means, the logically connected and latched switch means and the logically connected and unlatched switch means of two BICPU microcomputers in a logical bimemory "S" hookup.

FIG. 15 represents the FLT-1 mode.

FIG. 16 represents the FLT-2 mode.

FIG. 17 represents the FLT-3 mode.

FIG. 18 is a diagram depicting one way one ILU load can be logically connected to, and logically disconnected from, the "BRQ" circuit, and how the "BEN" and "BRQ" circuits of one ILU, can be logically connected to the "BEN" and "BRQ" circuits of the "B" and "C" bus circuits.

FIG. 19 is a detailed diagram of a BICPU microcomputer.

FIG. 20 is an illustration of BICPU microcomputers connected along dedicated standard Bimemory Interconnecting Control-BUS (BIC-BUS) circuits connected to "B" and "C" bus circuits, 522 and 524 of FIG. 19.

FIG. 21 is another illustration of BICPU microcomputers connected along dedicated BIC-BUS circuits connected to "B" and "C" bus circuits.

FIG. 22, FIG. 23, and FIG. 24 illustrate how a given multi-microcomputer system of BICPU microcomputers interconnected on sets of dedicated BIC-BUS circuits can be easily changed and modified, where both BICPU microcomputers and sets of dedicated BIC-BUS circuits can be added, that can contain additional "parallel" programs, without changing the program logic of the original system.