MICROCOMPUTER WITH DISCONNECTED, OPEN, INDEPENDENT, BIMEMORY ARCHITECTURE, ALLOWING LARGE INTERACTING, INTERCONNECTED MULTI-MICROCOMPUTER PARALLEL SYSTEMS ACCOMMODATING MULTIPLE LEVELS OF PROGRAMMER DEFINED HIERARCHY
Summary of the Invention
The invention is a Bimemory Independent CPU (BICPU) microcomputer which is comprised of a known CPU chip provided with additional circuitry to enable the CPU to interact in a multi BICPU microcomputer system. Each BICPU microcomputer in a system is supplied with an assigned standard memory mechanically and logically connected to it's BICPU's "A" bus circuits. The BICPU microcomputer is also provided with connectors enabling the CPU to be connected to system buses. Any number of BICPU microcomputers can be logically chained, linked and treed in a simple logical bimemory independent pattern infinitely in as many dimensions as is reasonably desired, using one standard set of dedicated, simple, single line conductors (system buses) to mechanically interconnect any "B" or "C" bus circuits of two different BICPU microcomputers. Packaging considerations will tend to be the limiting factor in the number of BICPU microcomputers that can be mechanically interconnected in large multi-BICPU microcomputer systems.
For example, the BICPU microcomputer system might be as small as a single stand alone application of one Bimemory Independent CPU microcomputer utilizing its given memory, to a system with thousands of Bimemory Independent CPU microcomputers (BICPU microcomputers) in a world weather prediction system, or in an oil field geological survey, or in the Strategic Defense Initiative Organization computer system.
The invention can be retrofitted on certain types of highly successful microcomputers with dedicated pinout circuits being built today so that most, if not all, of the present software of these highly successful microcomputers can be run on the new Bimemory Independent CPU microcomputer invention with very little, if any, modifications. The memory access circuits (address, data, control) of the CPU are connected to a switching unit. Three buses, "A", "B" and "C" are connected to the switching unit. The internal structure of the switching unit is configured solely by the CPU to create a signal path connecting the memory access circuits of the CPU to the desired bus or buses or any selected portion thereof.
The CPU is further provided with circuitry, including two dedicated function processors (ILUs), to enable the CPU to communicate and interact with other CPUs on either of the system buses "B" or "C". The CPU is also provided with additional registers to store switching unit configurations, system addresses etc.
This specification describes how the invention can be retrofitted on the MCS6502 microcomputer of the MCS650X chip family made by MOS Technology Inc. of Norristown, Pennsylvania, and described in detail in a HARDWARE MANUAL and a SOFTWARE MANUAL published in 1976, MOS Technology Inc. of Norristown, Pennsylvania, and incorporated herein by reference.
The CPU of the BICPU microcomputer invention has dedicated circuits similar to the MCS6502 type microcomputer as described in the MOS microcomputer HARDWARE MANUAL above. For example the MCS6502 and the MCS650X family of microcomputers are packaged in 40 pin DIPs (Dual In-Line Packages). According to FIG. 1.15, page 42, of the above MOS microcomputer HARDWARE MANUAL, there are 8 dedicated pins connected to the 8 Data Bus circuits, 8 dedicated pins connected to the 8 Address Bus Low circuits, 8 dedicated pins connected to the 8 Address Bus High circuits, 10 dedicated pins connected to computer and memory control circuits, 3 dedicated pins connected to Power circuits and 3 pins are not connected.
On Page 5 of the above MOS microcomputer HARDWARE MANUAL, in FIG. 1.1, the basic organization of a microcomputer system is shown based on the MCS6502 type microcomputer. Especially note that the *** MCS6502 *** microcomputer in the lower right in FIG. 1.1, is directly and independently connected to the dedicated standard memory circuits, (address bus, data bus, write enable, interrupts and other control signals).
On Page 41, in lines 9 through 11, of the above MOS microcomputer HARDWARE MANUAL, the MCS6502 has the oscillator and clock driver on-chip, thus eliminating the need of an external high-level two-phase clock generator.
