MICROCOMPUTER WITH DISCONNECTED, OPEN, INDEPENDENT, BIMEMORY ARCHITECTURE, ALLOWING LARGE INTERACTING, INTERCONNECTED MULTI-MICROCOMPUTER PARALLEL SYSTEMS ACCOMMODATING MULTIPLE LEVELS OF PROGRAMMER DEFINED HIERARCHY
Therefore with the MCS6502, in FIG. 1.1 of the MOS microcomputer HARDWARE MANUAL above, the microcomputer independently, directly, logically controls all of the Program Memory (ROM), the Data Memory (RAM), and the Peripheral Interface Device shown, by independently, directly, logically reading and independently, directly, logically writing to the dedicated standard memory circuits mechanically and logically connected to the 40 pins of the MCS6502 Pinout Designation as shown in FIG. 1.15 on page 42 of the above MOS microcomputer HARDWARE MANUAL.
The MCS6502 is a CPU that can independently, directly, logically read or write, in a logical manner, 256 pages of 256 characters each, where each character can be any of 256 different characters. The phrase, in a logical manner, is meant to include all of the CPU's present and potential set of microinstructions, which in the case of the MCS6502 consists of 256 different microinstructions of which essentially 156 have been implemented.
The MCS6502 independently, directly, logically controls everything that is read or written on these 256 pages of memory space.
Examples of fantastic implementations of the MCS6502 include the Commodore, Apple, Atari, and many other personal computers. The MCS6502 essentially is an 8-bit microcomputer addressing a 16-bit address space. (With essentially 16-bit MCS650X type microcomputers addressing a 32-bit address space, the numbers 256 above can be changed to 65,536. In the World Climate and SDIO problems above, 16-bit BICPU microcomputers addressing 32-bit address space can be used).
The BICPU microcomputer invention takes the MCS6502 and the dedicated address, data and control circuits presently connected to the 40 pins in FIG. 1.15 on page 42 of the MOS microcomputer HARDWARE MANUAL (or some other similar type highly successful microcomputer), and defines these circuits the "A" bus circuits 520 of FIG. 19 (the power circuits are not changed by the invention and for clarity are not shown in FIG. 19). The new bimemory switching circuits 502, 504, 506, and 508, of FIG. 19 are inserted in these "A" bus circuits between the CPU and the pins of FIG. 1.15 on page 42 above, (but are not inserted in the BICPU microcomputer power circuits). These bimemory switching circuits are also connected to the "B" bus circuits 522, and the "C" bus circuits 524 in a bimemory manner where at any one time the individual address circuits, data circuits and the read/write circuit from the microcomputer of FIG. 1.1 page 5, is logically directly connected to only one of the dedicated off chip pins in the "A" bus circuits 520, "B" bus circuits 522 or "C" bus circuits 524. The remainder of the circuits utilized for memory control, e. g. clock timing circuits, ready circuit, sync circuit, interrupt circuits etc., remain connected between the CPU and its memory during bimemory operations.
